ASIC Design Engineer - P Chappel Associates : Job Details

Our client is a late-stage start up based in New York City. They are expanding for their next major round of development. They hold numerous patents and have patents pending for their proprietary technology and computer architecture. This is an outstanding opportunity for ASIC Design Engineers to work in a dynamic environment with renowned experts.The ASIC Design Engineers will design and implement a state of the art SOC ASIC for this revolutionary new computer architecture.Duties include:

Logic design using Verilog / System Verilog

FPGA implementation and testing

Timing closure

IP selection and integration

Floor planning

CAD tool selectionMinimum Requirements:

BSEE or MSEE

5+ years of relevant experience

Experience writing Verilog or other HDL

TCL or other scripting language experience, programming in C or similar languages

Understanding of computer architecture

Track record of getting things done and solving problems

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