Physical Design Engineer Intern - Ambarella : Job Details

The Physical Design intern will support the physical design team with all aspects of physical design implementation and verification of Ambarella's cutting edge SoC for sub-28nm technology node.

The Physical Design Intern will support the following areas within the physical design team; floor-planning, auto place and route, physical implementation, timing verification, signal integrity analysis, power analysis, formal verification, and physical layout verification at block and/or full chip level.

Requirements

* BS/MS in EE/computer science with prior internship experience in physical design

* Good understanding in VLSI digital design/Layout/Timing closure

* Programming and scripting (C++, Perl, TCL)

* Basic knowledge on circuit design, device delays, and timing at gate-level

* Project work experience using UNIX

* Familiar with industry EDA tools such as Cadence SoC Encounter, Synopsys ICC/Primetime, Magma Talus/Blast, and Mentor Calibre.

* Hardware Design Languages like Verilog, VHDL

* Self-motivated team worker, good verbal and written communication skills.

* Experience with Cadence Encounter/RTL compiler/Conformal/QRC would be an added advantage.

* Solid understanding of hierarchical physical design strategies, methodologies and deep sub-micron technology issues

* Proven track record of delivering tape-out quality GDSII with silicon success is a plus.