Job Location : San Jose,CA, USA
Strativ is excited to work with a well established consultancy based in San Jose, CA who are on the lookout for a Senior Validation Systems Engineer a 12 Month Contract.
Job Title: FPGA Engineer - Senior Validation Systems
Join a leader in platform security and ransomware detection for cloud datacenters, 5G, and disaggregated compute ecosystems. The FPGA Engineer will focus on design verification, debugging, and system integration, working closely with Architecture, Verification, ASIC Design, and Software teams.
Responsibilities:
Set up FPGA/Emulation platforms (e.g., Synopsys HAPS) and device modeling.
Customize SOC design for FPGA platforms.
Support modeling, debugging, verification, and software development.
Collaborate with cross-functional teams for early prototyping and issue resolution.
Assist in test program development, chip validation, and production maturity.
Qualifications:
Strong experience with FPGAs and tools like Vivado.
Familiarity with SOC blocks (PCIe, USB, Ethernet, SPI, CPU).
Experience with Synopsys HAPS FPGA systems preferred.
Excellent communication skills.
BS or MS in EE/EECS/CS or related field.
5+ years of relevant experience.
If this is of interest please apply or share a up to date resume with ...@strativgroup.com